How would you ammend the following vhdl code so that when a

How would you ammend the following vhdl code so that when a switch is turned on the associated LEDs will light up in a sequence?

Solution

In the following code we need to light up LED in a sequence so we will change code as following. library IEEE; use IEEE.std_logic_1164.all; entity problem is port(switch_1,switch_2,switch_3 ,clock_1 : in std_logic; led1,led2,led3,led4,led5,led6,led7,led8,led9,led10,led11,led12,led13,led14,led15,led16 : out std_logic); end problem; architecture func of problem is begin process(switch_1,switch_2,switch_3,clock_1) begin variable counter : integer := 0; if(switch_1=\'1\')then if rising_edge(CLOCK_1) then counter := counter + 1; if counter =1 then; led1 <=\'1\'; else if counter =2 then; led8 <=\'1\'; else if counter =3 then; led10 <=\'1\'; else if counter =4 then; led12 <=\'1\'; else if counter =3 then; led16 <=\'1\'; else count := \'0\'; endif elsif(switch_2=\'1\')then if rising_edge(CLOCK_1) then counter := counter + 1; if counter =1 then; led4 <=\'1\'; else if counter =2 then; led5 <=\'1\'; else if counter =3 then; led6 <=\'1\'; else if counter =4 then; led7 <=\'1\'; else if counter =3 then; led11 <=\'1\'; else count := \'0\'; endif elsif(switch_3=\'1\')then if rising_edge(CLOCK_1) then counter := counter + 1; if counter =1 then; led2 <=\'1\'; else if counter =2 then; led9 <=\'1\'; else if counter =3 then; led13 <=\'1\'; else if counter =4 then; led14 <=\'1\'; else if counter =3 then; led15 <=\'1\'; else count := \'0\'; endif end if; end process; end func;
How would you ammend the following vhdl code so that when a switch is turned on the associated LEDs will light up in a sequence?Solution In the following code w

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