Answer die questions that follow the VIIDI code given below

Answer die questions that follow the VIIDI. code given below. LIBRARY iece USE lece std_logie_1164_ALL; ENTITY count IS PORTlcp, (ep, n_rd, n_pl, n_ce, u_d pL_data q END count; ARCITTECTURE are OF count IS BEGIN PROCESS (ep n_nd, n_pl) BEGIN IF (n_rd = \'0\' AND n_pl - \"I\") THEN ELSIF (n_rd - \'1\' AND n_Pl = 0) THEN q pl_data; ELSIF (ep EVENT AND cp= \'1\') THEN IF (n_ce- \'0\') THEN IF (u_d = \'0\')THEN ELSE ENF IF; END IF; END IF; END PROCESS; END are Which of the inputs are asynchronous? What is the purpose of input n_ce? Assume_n_rd = 1, n_pl= 1, n_ce = 1 u_d = 1 pl_data = 15 and q_9 then a clock event triggers the execution of the PROCESS. What will the value of q be after the PROCESS executes? What is the MOD number for this counter?

Solution

a ) Inputs in the process statement are called asynchronous inputs. So asynchronous are cp, n_rd and n_pl.

b) Input \"n_ce\" is used to latching of output signal.

c) n_rd=1, n_pl=1, n_ce=1, u_d=1, pl_data=15 and q=9. Then clock occurs and cp=1. Then Output if latches the previous output. So output will be \"q=9\".

d) It is a MOD 16 UP and DOWN counter. Because pl_data gives the infromation about starting of counter.